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PLL205-01
Motherboard Clock Generator for AMD - K7
FEATURES
* * * * * * * * * * Generates all clock frequencies for VIA K7 chip sets requiring multiple CPU clocks and high speed SDRAM buffers. Support one pair of differential CPU clocks, one open-drain CPU, 6 PCI and 13 high-speed SDRAM buffers for 3-DIMM applications. One 24_48MHz clock and one 48MHz clock. Two14.318MHz reference clocks. Power management control to stop CPU, and Power down Mode from I2C programming. Support 2-wire I2C serial bus interface with builtin Vendor ID, Device ID and Revision ID. Single byte micro-step linear Frequency Programming via I2C with Glitch free smooth switching. Spread Spectrum 0.25% center spread, 0 to -0.5% downspread. 50% duty cycle with low jitter. Available in 300 mil 48 pin SSOP.
PIN CONFIGURATION
VDD0 REF0//CPU_STOP#^ GND XIN XOUT VDD1 PCI5/MODE*^ PCI0/FS3*^ GND PCI1/SEL24_48*^ PCI2 PCI3 PCI4 VDD2 SDRAMIN GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
REF1/FS2*^ GND CPUT1 GND CPUC0 CPUT0 VDD3 PD#^ SDRAM12 GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0*^ 24_48MHz/FS1*^
Note: ^: Pull up, #: Active Low *: Bi-directional latched at power-up
PLL205-01
BLOCK DIAGRAM I/O MODE CONFIGURATION
MODE (Pin 7)
VDD1 XIN XOUT XTAL OSC REF(0:1)
PIN 2 REF0 CPU_STOP
1 (OUTPUT) 0 (INPUT)
CPUT(0:1)
POWER GROUP
* * * * * VDD0: PLL CORE VDD1: REF(0:1), XIN, XOUT VDD2: PCI(0:5) VDD3: SDRAM(0:12) VDD4: 48MHz, 24_48MHz
SDATA SCLK FS (0:3)*
I2C Logic Control Logic
CPUC0
VDD2 PCI(0:4) PLL1 SST PCI5 VDD4 48Mhz PLL2
PD
KEY SPECIFICATIONS
* * * * * CPU Cycle to Cycle jitter: 250ps. PCI to PCI output skew: 500ps. CPU to CPU output skew: 175ps SDRAM to SDRAM output skew: 250ps. CPU to PCI skew (CPU leads): 0 ~ 3 ns.
/2
24_48Mhz VDD3 SDRAM(0:11)
SDRAMIN SDRAM12
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 1
PLL205-01
Motherboard Clock Generator for AMD - K7
PIN DESCRIPTIONS
Name
VDD0 VDD1 VDD2 VDD3 VDD4 GND XIN XOUT REF0//CPU_STOP
Number
1 6 14 19,30,36,42 27 3,9,16,22, 33,39,45,47 4 5 2
Type
P P P P P P I O B Power supply for PLL CORE.
Description
Power supply for REF0, REF1, and crystal oscillator. Power supply for PCI (0:5). Power supply for SDRAM (0:12). Power supply for 24_48MHz and 48MHz. Ground. 14.318MHz crystal input that has internal loads cap (36pF) and feedback resistor from XOUT. 14.318MHz crystal output. It has internal load cap (36pF). Multiplexed pin controlled by MODE signal. When CPU_STOP is low, it will halt CPUT (0:1), CPUC0 and SDRAM (0:11) outputs. In output mode, this pin will generate buffered reference clock output. At power-up, MODE function will be activated. When MODE is Low, Pin 2 is input for CPU_STOP. When high, Pin 2 is output for REF0. After input data latched, this pin will generate PCI bus clock. At power-up, this pin is input pin and will determine CPU clock frequency. After input sampling, this pin will generate output clocks. FS3 has internal pull up (high by default). At power-up, this pin will select 24MHz (when high) or 48MHz (when low) for pin25 output. After input sampling, this pin is PCI output. It has internal pull up resistor. PCI clock outputs. Buffer input pin: The signal provided to this input pin is buffered to 13 SDRAM outputs. SDRAM clock outputs, Fan-out Buffer outputs from SDRAMIN pin.
PCI5/MODE
7
B
PCI0/FS3
8
B
PCI1/SEL24_48 PCI(2:4) SDRAMIN SDRAM(0:11) SDATA SCLK 24_48MHz/FS1, 24MHz/FS0 SDRAM12 PD# CPUT(0:1) CPUC0 REF1/FS2
10 11,12,13 15 17,18,20,21,28, 29,31,32,34,35, 37,38 23 24 25,26 40 41 43,46 44 48
B O I O B I B O I O O B
Serial data inputs for serial interface port. At power-up, these pins are input pins and will determine the CPU clock frequency. FS0, FS1 have internal pull up (high by default). When CPU_STOP is low, this pin is still free running. When the power down is low, this SDRAM will be stopped. When low, it will stop all clock outputs. It has internal pull-up resistor. "True" clocks of differential pair open-drain CPU outputs. "Complementary" clocks of differential pair open-drain CPU outputs. Buffered reference clock output after input data latched during power-up.
Rev 03/07/00 Page 2
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
PLL205-01
Motherboard Clock Generator for AMD - K7
FREQUENCY (MHz) SELECTION TABLE
I2C Byte0 Bit2 FS3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU
124.0 75.0 83.3 66.8 103.0 112.0 133.3 100.0 120.0 115.0 110.0 105.0 140.0 150.0 124.0 133.3 90.0 92.5 95.0 97.5 101.5 127.0 136.5 100.0 120.0 117.5 122.0 107.5 145.0 155.0 130.0 133.3
PCI
41.3 37.5 41.7 33.4 34.3 37.3 44.4 33.3 40.0 38.3 36.7 35.0 35.0 37.5 31.0 33.3 30.0 30.8 31.7 32.5 33.8 42.3 34.1 33.3 40.0 39.2 40.7 35.8 36.3 38.7 32.5 33.3
Spread Spectrum Modulation
0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0 to -0.5% 0 to -0.5% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0 to -0.5%
0 default
1
POWER MANAGEMENT
CPU_STOP 0 1 CPUC0 Stopped Low Running CPUT (0:1) Stopped Low Running SDRAM (0:11) Stopped Low Running SDRAM12 Running Running CRYSTAL Running Running VCO Running Running
Rev 03/07/00 Page 3
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
PLL205-01
Motherboard Clock Generator for AMD - K7
POWER MANAGEMENT (Continued)
PD 0 1 CPUC0 Stopped Low Running CPUT (0:1) Stopped Low Running SDRAM (0:11) Stopped Low Running SDRAM12 Stopped Low Running CRYSTAL Stopped Running VCO Stopped Running
I2C BUS CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _
Provides both slave write and readback functionality Standard mode at 100kbits/s The serial bits will be read or sent by the clock driver in the following order Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at power-up is = (0x09).
Serial Bits Reading
Data Protocol
I2C CONTROL REGISTERS
1. BYTE 0: Functional and Frequency Select Clock Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
8 48 25 26 -
Default
0 1 0 0 0 0 1 0
Description
FS3 ( see Frequency selection Table ) FS2 ( see Frequency selection Table ) FS1 ( see Frequency selection Table ) FS0 ( see Frequency selection Table ) Frequency selection control bit 1=Via I2C, 0=Via External jumper FS4 ( see Frequency selection Table ) 0=Normal 1=Spread Spectrum enable 0=Normal 1=Tristate Mode for all outputs
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 4
PLL205-01
Motherboard Clock Generator for AMD - K7
BYTE 1: CPU Clock Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
40 43,44 46
Default
1 1 1 1 1 1 1 1
Description
Reserved Reserved Reserved Reserved SDRAM12 ( Active/Inactive ) Reserved CPUT0, CPUC0 ( Active/Inactive ) CPUT1 ( Active/Inactive )
3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
7 13 12 11 10 8
Default
1 1 1 1 1 1 1 1
Description
Reserved PCI5 ( Active/Inactive ) Reserved PCI4 ( Active/Inactive ) PCI3 ( Active/Inactive ) PCI2 ( Active/Inactive ) PCI1 ( Active/Inactive ) PCI0 ( Active/Inactive )
4. BYTE 3: SDRAM Clock Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
26 25 17 18 20 21
Default
1 1 1 1 1 1 1 1
Description
Reserved Reserved 48MHz ( Active/Inactive ) 24_48MHz ( Active/Inactive ) SDRAM11 ( Active/Inactive ) SDRAM10 ( Active/Inactive ) SDRAM9 ( Active/Inactive ) SDRAM8 ( Active/Inactive )
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 5
PLL205-01
Motherboard Clock Generator for AMD - K7
5. BYTE 4: SDRAM Clock Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
28 29 31 32 34 35 37 38
Default
1 1 1 1 1 1 1 1
Description
SDRAM7 ( Active/Inactive ) SDRAM6 ( Active/Inactive ) SDRAM5 ( Active/Inactive ) SDRAM4 ( Active/Inactive ) SDRAM3 ( Active/Inactive ) SDRAM2 ( Active/Inactive ) SDRAM1 ( Active/Inactive ) SDRAM0 ( Active/Inactive )
6. BYTE 5: Peripheral Clock Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
48 2
Default
X X X X 1 X 1 1
Description
Inverted Power-up latched FS3 value (Read only) Inverted Power-up latched FS2 value (Read only) Inverted Power-up latched FS1 value (Read only) Inverted Power-up latched FS0 value (Read only) Reserved Inverted Power-up latched SEL24_48MHz value (Read only) REF1 ( Active/Inactive ) REF0 ( Active/Inactive )
7. BYTE 6: Revision ID and Vendor ID Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
-
Default
0 0 0 0 0 0 1 1
Description
Revision ID Bit 3* Revision ID Bit 2* Revision ID Bit 1* Revision ID Bit 0* Vendor ID Bit 3* Vendor ID Bit 2* Vendor ID Bit 1* Vendor ID Bit 0*
Note: *: Default value at power-up
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 6
PLL205-01
Motherboard Clock Generator for AMD - K7
8. BYTE 7: Linear Programming (M) Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
-
Default
0 0 0 0 0 0 0 0
Description
Linear programming sign bit ( 0 is "+", 1 is "-" ) Linear programming magnitude bit 6 (MSB) Linear programming magnitude bit 5 Linear programming magnitude bit 4 Linear programming magnitude bit 3 Linear programming magnitude bit 2 Linear programming magnitude bit 1 Linear programming magnitude bit 0 (LSB)
9. BYTE 8: Device ID Register (1=Enable, 0=Disable) Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin#
-
Default
0 0 0 0 0 0 1 0 Reserved Device ID Bit 6* Device ID Bit 5* Device ID Bit 4* Device ID Bit 3* Device ID Bit 2* Device ID Bit 1* Device ID Bit 0*
Description
Note: *: Default value at power-up
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 7
PLL205-01
Motherboard Clock Generator for AMD - K7
PROGRAMMING OF CPU FREQUENCY To simplify traditional loop counter setting, the PLL205-01 device incorporates SMART-BYTE TM technology with a single byte programming via I2C to better optimize clock jitter and spread spectrum performance. Detail of PLL205-01's dual mode frequency programming method is described below: 1. ROM-table Frequency Programming: The pre-defined 32 frequencies found in Frequency table can be accessed either through 5 external jumpers or by setting internal I2C register in BYTE0. 2. Micro-step Linear Frequency Programming: CPU Frequency can be programmed via I2C in fine and linear positive or negative stepping around selected CPU frequency in Frequency table. The highest step is either +127 or -127. Other bus frequencies will be changed proportionally with the rate that CPU frequency change. The formula is as follow:
F CPU = F CPU.ROM-Table (=0.22)* M
Where: 1. M is magnitude factor defined in I2C Byte 7.bit(0:6) 2. (sign bit) of M is defined in I2C Byte7.bit 7 3. is a constant = 0.22
FREQUENCY PROGRAMMING EXAMPLE: 1. Procedures to program target CPU frequency to 139.0 Mhz:
A. Locate the closest CPU frequency from Frequency-ROM table: 136.5 B. = 0.22 C. Solve M (Linear Magnitude factor) in integer: M = (F CPU - F CPU - ROMTABLE ) / = (139 - 136.5) / 0.22 = 11 D. Program I2C register: 7 6 5 4 3 2 1 0
0
7
1
6
1
5
0
4
1
3
1
2
0
1
0
0
Setting of I2C.BYTE0 Setting of M = +11 in I2C.BYTE7
FS3 FS2 FS1 FS0 CTR FS4
0
0
0
M5
0
M4
1
M3
0
M2
1
M1
1
M0
Sign M6
F CPU = 136.5 + (0.22) * 11 = 138.92 ( % of frequency increased = 1.8 % ) F PCI = 34.1 * (1+1.8%) = 34.7
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 8
PLL205-01
Motherboard Clock Generator for AMD - K7
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature ESD Voltage
SYMBOL
V DD VI VO TS TA TJ
MIN.
V SS -0.5 V SS -0.5 V SS -0.5 -65 0
MAX.
7 V DD +0.5 V DD +0.5 150 70 115 2
UNITS
V V V C C C KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. AC/DC Electrical Specifications PARAMETERS
Input High Voltage Input Low Voltage Input High Current Input Low Current
SYMBOL
V IH V IL I IH I IL1
CONDITIONS
MIN.
2.0 VSS-0.3
TYP.
MAX.
VDD+0.3 0.8 5
UNITS
V V uA uA
V IN = V DD Logic inputs without internal pull-up on SCLK, VIN = 0V Logic inputs with internal pull-up resistors, VIN = 0V Pin 2,7,8,10,25,26,48 CL=0 pF @ 66MHz CL=0 pF @ 100MHz CL=0 pF @ 133MHz VDD = 3.3V Logic Inputs XIN & XOUT pins 27 12 14.318 -5
Input Low Current Power Down Pull-up resistor Operating Supply Current Input frequency Input Capacitance
I IL2 PD Rpu IDD FI CIN CINX
-200 600 120 180 16 5 45
uA uA Kohm mA Mhz PF PF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 9
PLL205-01
Motherboard Clock Generator for AMD - K7
2. Output Buffer Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V5%, and ambient temperature range TA= 0C to 70C
PARAMETERS
SYMBOL
OUTPUTS
CPU (Open Drain) REF(0:1)
CONDITIONS
Measured @ 0.3V ~ 1.2V, CL=20pf, 3.3V5% Measured @ 0.4V ~ 2.4V, CL=20pf, 3.3V5% Measured @ 0.4V ~ 2.4V, CL=30pf, 3.3V5% Measured @ 0.4V ~ 2.4V, CL=20pf, 3.3V5% Measured @ 1.2V ~ 0.3V, CL=20pf, 3.3V5% Measured @ 2.4V ~ 0.4V, CL=20pf, 3.3V5% Measured @ 2.4V ~ 0.4V, CL=30pf, 3.3V5% Measured @ 2.4V ~ 0.4V, CL=20pf, 3.3V5% VT = 50% VT = 1.5V
MIN.
TYP.
MAX.
0.9 4
UNITS
Output Rise time
T OR PCI(0:5) 24_48MHz, 48MHz CPU (Open Drain) REF(0:1)
ns 2 4 0.9 4 ns 2 4
Output Fall time
T OF PCI(0:5) 24_48MHz, 48MHz REF(0:1),CPU, PCI(0:5) 24_48MHz, 48MHz CPU to CPU
Duty Cycle
DT
45
55 200
%
Clock Skew
T SKEW
PCI to PCI CPU to PCI CPU to AGP CPU PCI(0:5)
VT = 50%
200 0 -500 3 500 50 30 40 40 40
ps
ns
VO = VX
Output Impedance
Z0
REF(0:1) REF1 24_48MHz, 48MHz
VDD=3.3V5%
Ohm
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 10
PLL205-01
Motherboard Clock Generator for AMD - K7
2. Output Buffer Electrical Specifications, continued
Unless otherwise stated, all power supplies = 3.3V5%, and ambient temperature range TA= 0C to 70C
PARAMETERS
SYMBOL
CPU
OUTPUTS
REF(0:1)
CONDITIONS
MIN.
TYP.
MAX.
-22
UNITS
Output High Current
I OH
PCI(0:5) 24_48MHz 48MHz CPU REF(0:1)
VOH = 2.0V
-16 -22 -22
mA
VOL = 0.4V
20 16
Output Low Current
I OL
PCI(0:5) 24_48MHz 48MHz
VOL = 0.8V
19 16 16
mA
Jitter, One Sigma Jitter, Absolute
J sigma JAbs
REF,48MHz,24MHz CPU REF,48MHz,24MHz CPU PCI
VT = 1.5V VT = 50% VT = 1.5V VT = VX Measured @ 1.5V 0.4 -250 -1
0.5 250 1 250 250 Vpullup +0.6 Vpullup +0.6 1100
ns ps ns ps V V mV
Jitter (cycle to cycle) AC Differential Voltage DC Differential Voltage Differential Crossover Voltage
J cyc-cyc VDIF VDIF VX
CPU (Open Drain)
0.2 550
Note: Vpullup = 1.5V (external); VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 11

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